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@cstanhope

They have no one to blame but themselves - asking for a chip with almost four times less LUTs (maximum 7680) for a price more than ten times more than the Chinese Tangnano25k board, which also holds 25000 LUTs (more than three times ).

@yrabbit You're right about the boards. I haven't tried to price their parts in any sort of volume, but if there is a similar price difference, then yikes!

@yrabbit I dug up an old invoice. Back in 2015 I was able to get that icestick board for $21.86. Hmm...

@cstanhope
Of course it is possible to conduct research in large volumes, but from the times of the institute I remember that a random sample is usually indicative. I tried again and the result is even worse: 138000 LUTs vs 5300 LUTs.

I should note that the number of LUTs is such a clear indicator, but also the other board components are not in favour of Lattice - the oldest Tangnano models (even those that are no longer in production) run at a minimum of 27MHz

@cstanhope
(and have this quartz on the board), Tangmega 138k at a minimum of 50MHz. The iCE40 is 12MHz.

The fact that you were able to buy an iCE40 in 2015 at a reasonable price (although it depends on how you look at it - you see I don't quote prices for boards of similar power:) ) tells me that their irresponsible and unwise pricing policy in the following years led to the current state of affairs.

@cstanhope @yrabbit They have some open source tools to use to program this fpga?
YRabbit

@diegor @cstanhope

Not ‘they’, but yes the fully open source toolkit is there - github.com/YosysHQ/apicula

Also Gowin itself has a ‘student’ version designed to support 3 types (or families, I can't remember) of FPGAs and in addition the fully licensed version requires only registration on the website.

gowinsemi.com/en/support/home/

GitHub - YosysHQ/apicula: Project Apicula 🐝: bitstream documentation for Gowin FPGAs

Project Apicula 🐝: bitstream documentation for Gowin…

GitHub
Nov 22, 2024, 06:25 · · · Web · 0 · 2