``Lost forgotten technologies,'' Donovan said. He sighed and tossed the cassettes to his bed. ``Our remote ancestors poked reeds into mud and baked mud into brick. We can still read those ancient thoughts, millennia later. But it seems that the greater the technology, the more ephemeral it becomes.''
I had to be careful in my wishes🙂
Open drain, open drain, open drain, do not forget to switch the #fpga pins to open drain otherwise silicon heaven will receive new citizens.🙂
I move on. The start is checked, as well as every bit of the input address of the slave device.
The verification code is already significantly larger than the actual working code.
What is left... the R/W bit, the STOP condition and I need to come up with something with the processing of ACK.
During the reset, a mess was going on with the signals, so I now brought them to a more or less acceptable form: if the front of the SDA overtakes SCL, this will be a STOP condition, which is permissible. If on the contrary, it’s just a crazy data bit that is completely different from the START condition, which is permissible too.
- what the heck is glamor ?
- opengl 2d acceleration. It calls GL functions to render to the texture directly. It's somehow hardware independent.
- I love that. 'somehow'
I forgot to write posedge in the
and went crazy for half a day trying to find where I suddenly formed a logical cycle.😂
sda is changing only when scl=0
if (o_scl && $stable(o_scl)) begin
it kind of goes through formal verification, but now I have a different problem: I do not believe this verification🙂
What bothers me is that the sda changes along the front when scl goes from 0 to 1. Maybe this is wrong.
@alcinnz if there's anything I've learned implementing my own forth, more people should try weird, out-there languages they've never tried before
It is not very pleasant that it is silent and the HDD led doesn't blink.
@yrabbit Yeah, I'm in the camp of "If your langauge requires braces around multi-statement blocks, then braces should always be required." and then pretend that's true when I'm writing my code.
Although, I admit to eliding begin/end off of some of my verilog code. :/
￼Enthusiastic programmer. ￼Love CRPGs, black currant, summer and blinking LEDs. ￼Villager. Planted an oak tree. ￼#dragonflybsd desktop
!Extremely dumb persons, Nazis and Russophobes will be blocked without notice!
"I appreciate SDF but it's a general-purpose server and the name doesn't make it obvious that it's about art." - Eugen Rochko