I might need some help from smart people who Actually Know Electronics™ soon. I want to build new memory modules for the 3B2 computer, since you can't find them for love or money. Unfortunately, a reliable source for 5V asynchronous DRAM ICs is unobtainium now, so I'd like to design a replacement around SRAM. Latching the RAS and CAS lines with the right timings sounds trickier than anything I've done to this point. Help?


I mean, unless someone REALLY clever knows how to design a DDR DRAM replacement, but since there's no clock running to the memory, I assume that's impossible.

@twylo You could make a complex board with an onboard clock generator, but it probably isn't worth the effort.

Is there a reference for the timings seen on the 3B2? Do you have part numbers for the DRAMs it uses?

A DRAM-ish wrapper around an SRAM shouldn't be too difficult. The key is that you need latches, which are clocked by RAS and CAS: they are strobes, which are clocks by another name.


@EdS Thanks for these pointers! A colleague of mine has a board design using a 72 pin SIMM adapter. The major advantage there seems to be that 72 pin SIMMs are relatively cheap on the used market, and are basically a drop-in with no extra glue logic needed. A kludge, perhaps? But maybe the best idea.

@twylo how much memory? Perhaps an FPGA would be a good solution. An FPGA has internal memory that can replace the DRAM, depending on the amount needed, and the logic blocks necessary to latch the address using RAS and CAS. The biggest difficultly is likely the power supply as FPGAs generally want 3.3V or less Vcc. The I/O might be 5V tolerant for some devices, and open-drain outputs with pull ups might work if timing isn’t tight.
@twylo oh, and I might have some older (1990ish) DRAM ICs about. I’ll try to dig through my stash in the next day or two to see.
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