ｂｉｔｏｆｈｏｐｅ @bitofhope@mastodon.sdf.org

"Illium" was another name for the city of Troy

"-ad" is a suffix that can be used to mean "the story of"

Therefore "The Illiad" is properly translated as; drumroll please...

Troy Story

Understatement of the day "most of cookie banners are violating #GDPR" (not to mention simple honesty and common sense).

#LaptopRescue

Playing nethack on this Now Officially Rescued Sparc64 laptop is oddly satisfying!

One day, his god spoke to him.
"Go forth," his god said, "and find another god."
"I will not abandon you."
"You are my last believer."
"Others may lose faith, but-"
"I am very old, and so, so tired. Let me go."
"Oh."
"Please."
"Who speaks? Begone!"
"Thank y-" The god faded away.
#MicroFiction #TootFic #SmallStories #TypoCorrected

"DWeb". Really? Decentralized web isn't a new concept that we need to brand. It's what we had and then gave up. We don't need to brand it and come up with new definitions. We just need to take back what is rightfully ours.

Arcane systems lore and a parable about development, all in one. The point that impossible bugs tend to be dismissed until they recur frequently enough to prove they aren't impossible is a good one.

hoot: https://twitter.com/bcantrill/status/1135378456240373760

@bcantrill: Upon joining Sun in 1996, my first project in kernel development was to allow the operating system clock interrupt rate to be made more fine-grained. 1/

@bcantrill: Historically in Unix, this rate ("hz") was set to 100, yielding a 10ms timeout resolution. My work would allow it to be tuned to 1000, yielding a 1ms timeout resolution. 2/

@bcantrill: (Later, I would develop a subsystem that allowed for arbitrary resolution timers -- but that was still in the future in 1996.) 3/

@bcantrill: I thought it was a little lame that we were only allowing this to be tuned to 1000; why not allow someone to tune it to the point that the system was running only the clock interrupt? 4/

@bcantrill: So I allowed it to be arbitrary tunable -- and entertained myself by seeing how high I could set it before the system would no longer boot, executing nothing but the clock interrupt! 5/

@bcantrill: On one machine -- a 40 MHz sun4c -- I was able to tune this up to 26000 hz (!), at which point the box didn't boot. Perversely satisfied, I went home. 6/

@bcantrill: I came in the next morning and the machine was at the login prompt! The machine -- executing probably a single-digit number of instructions between clock interrupts -- had managed to finally boot! 7/

@bcantrill: I reflexively hit the carriage return on the serial line... 8/

@bcantrill: ...and the box rolled, panicking deep in the animal brain of interrupt handling. 9/

@bcantrill: It took me a little while to debug, but I ultimately determined that we were taking a level-10 clock interrupt AFTER the processor interrupt level (PIL) was set to 10 -- which should be impossible! 10/

@bcantrill: Of note, we were taking the interrupt on the instruction or two immediately after the "wrpsr" instruction to raise the PIL 11/

@bcantrill: Now, "wrpsr" is what the architecture manual calls a "delayed-write instruction" in that it can take up to 3 instructions to take effect -- but PIL is supposedly exempt from this 12/ https://pic.twitter.com/8j39y0Mt64

@bcantrill: Could it be possible that, in fact, the manual didn't accurately describe the CPU, and the write to PIL was subject to the same delayed-write effect? 13/

@bcantrill: As it turns out, this was exactly the case: the Sun Microelectronics folks were able to reproduce it, and determined that it was an issue on all Sun SPARC V7 (sun4c) and SPARC V8 (sun4m/sun4d) processors (!!) 14/

@bcantrill: Going back through the OS bug database, there were many, many undiagnosed instances of this bug -- which we dubbed "PIL tunneling" because it was evocative of quantum tunneling 15/

@bcantrill: All of those bugs had been closed out as not reproducible -- which, to be fair, they were 16/

@bcantrill: Fortunately, the fix was simple: recognize that we were in this impossible condition and return from interrupt without indicating end-of-interrupt, relying on the fact that the now-quiesced PIL would block the interrupt until PIL had been properly lowered 17/

@bcantrill: We did, however, add a counter in this case -- and in the years following, we essentially always found it to be horrifyingly non-zero! 18/

@bcantrill: The microprocessors that exhibited PIL tunneling are long gone, but its core lessons remain germane: 19/

@bcantrill: 1. Systems can work by accident (potentially for years!) 20/

@bcantrill: 2. Systems exhibit interesting behavior when pushed beyond their breaking point 21/

@bcantrill: 3. Systems that malfunction should be completely understood, even if the conditions under which they break seem synthetic or contrived 22/

@bcantrill: Discovering PIL tunneling was, in hindsight, an entirely apt beginning to a career spent at the hardware/software interface! 23/23