I collect a ton of 6502 asm notes/guides/tools/sources over at if you're interested in learning assembly:

github.com/neauoire/linux-note

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@neauoire Could there be a “multi core” 6502 array? Could a chip decide which of several 6502 will get a thread to munch on? Like, if everything in the data bus is addressed as normally, but then gets multiplexed across a 6502 array? Sort of like SuperCPU, I think.

@Shufei @neauoire the W65C134S variant includes built in serial networking that could be used for that.

@Shufei @neauoire the w65C265S seems especially designed for parallel processing applications

@Shufei @neauoire actually looking at the 134 closer, it seems *really* designed for parallel processing.

@Shufei @neauoire it includes for instance, pins dedicated to “chip select”, not sure what that means yet.

@Shufei @neauoire To get more exotic you could maybe have a big FPGA and dynamically program CPUs with arbitrary architectures to appear as needed. At times when you don't need much compute it could scale back to something very minimal and so conserve energy and reduce complexity, so higher reliability.

@Shufei 0_0 I don't know, I actually don't understand your question, it's too technical. I understand 6502 assembly, but I don't know anything about the electronics side aspect of it at the moment. Sorry :(

@Shufei @neauoire I seem to recall that the 6502 crashes if you stop it's clock (or run it too slowly), which might cause problems with this. I think maybe you'd need to feed the "idle" 6502s a synthetic stream of NOPs to keep them happy. In contrast, the Z80 is perfectly happy with arbitrarily slow clocking. You can even clock them by hand at sub-Hertz speeds with a switch! I found this very useful when building Z80 machines, you can stick LEDs on the pins and run the whole thing slowly enough to watch exactly what's happening on the buses, step by step.

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